1. Field of the Invention
This invention relates to a semiconductor testing device used in testing a semiconductor device.
2. Description of the Related Art
At the stage of shipping a semiconductor device (for example, a semiconductor memory device) a test for evaluating the characteristic of semiconductor device is performed (a characteristic evaluation test). In a conventional characteristic evaluation test, a testing method in which the same operation is repeated many times in all the areas of an a semiconductor memory device is adopted. That is, a test parameter value is changed in order, said test parameter value being specified by a test program which operates in the semiconductor testing device for a semiconductor memory which is to be tested (hereinafter written as “MUT”, which is an abbreviation of Memory Under Test). For example, when a read-out voltage is applied to all the areas, a test is repeated while stepping up little by little this applied voltage and the characteristics of the memory cells which comprise a semiconductor memory device are tested.
However, with the increase in capacity of a semiconductor device, the percentage of the whole test which is taken up by the characteristics evaluation test is increasing and the number of times itself which the same operation is performed while changing the conditions is also increasing dramatically. As a result, the required time for a test becomes larger and larger. Consequently, as is shown in U.S. Pat. No. 6,477,672-B1, an attempt to arrange a new memory within a semiconductor testing device which has a storage capacity corresponding to the number of memory blocks which an MUT has. However, by this method, the number of memory cell blocks in each MUT is different, there is a need to set a memory for each MUT and thus is not efficient.